- New 2014 Version of Ascent Lint HDL Analyzer and Rule Checker
- What is Driving Lint Usage in Complex SOCs?
- Ascent Lint Rule of the Month: OPEN_INPUT
- Ascent Lint HDL Rule of the Month: ZERO_REP
- When to Retool the Front-End Design Flow?
Early Verification Products
Ascent Lint is a state-of-the-art RTL linter and rule checker for full-chip SoC analysis. Designed from the bottom-up to deliver the highest performance, capacity and low-noise reporting, it is the best-in-class HDL linter available today with a comprehensive set of syntax and semantic checks.
Ascent Lint supports the Verilog, VHDL, and System Verilog languages and gate-level netlists.
The built-in rules ensure that designs meet requirements for correct and efficient synthesis, simulation, test, reuse, RTL/gate sign-off. Design reuse is enabled with rules for industry standards such as the Reuse Methodology Manual (RMM) and STARC.
Smart Rules for Verilog, VHDL, SystemVerilog, and Netlists detect:
- FSM state reachability and coding issues
- Legal but dubious modeling indicating probable errors
- Differences between simulation and synthesis semantics
- Naming and RTL coding conventions
- Subset restrictions to enforce modeling clarity and reduce complexity
- Opportunities to improve simulation performance
- Operations with hidden or expensive implementation costs
- Downstream tool flow issues
- Network and connectivity checks for clocks, resets, and tri-state-driven signals
- Module partitioning rules
- Design testability