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Benefits:
- Detects complex design bugs early in the design flow
- Finds design and coding guiding bottlenecks that impact simulation, synthesis, testability, and implementation costs
- Offers easy adoption, use and customization
- Integrates with Real Intent’s tools and plugs straight into standard EDA flows
- Helps geographically dispersed design teams to create higher quality designs
- Offers high return on investment
Features:
- Highest performance of any lint tool in the industry
- Low-noise, yet comprehensive violations report
- Fast and powerful debugging capability with cross probing to RTL design source; pinpoints the exact source of issues
- Offers rules from STARC Verilog and VHDL Policy, Verilog and System Veri-log Gotchas, Reuse Methodology Manual, Principles of Verifiable RTL Designs, DataPath Synthesis rules, and rules based on Real Intent industry expertise
- Provides GUI for rule selection, waiving, and customization as well as debugging the violations report
Ascent Lint Data Sheet:
 English  Japanese
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