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Benefits:
- Powerful sequential formal analysis quickly finds common functional errors in the design especially in early RTL stage
- Start analysis long before simulation can start
- Easy to use, easy setup and intuitive methodology
- Provides sufficient block level verification that longer cycles of chip level verification are avoided
- Verifies designs with complex state machines
Features:
- Convergence Formal Engine™ provides highest capacity and performance
- Provides full counter-examples in VCD format
- Fully automatic, requires no testbenches
- Leading-edge language support for VHDL, Verilog, SystemVerilog, and mixed languages
- Supports SystemVerilog SVA/VHDL PSL as constraints to improve accuracy of formal analysis
- Comprehensive analysis and reporting
- Root cause analysis minimizes debug!
Ascent IIV Data Sheet:
 English  Japanese
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