Unleash the Power of Formal Analysis for Clock Domain Crossing Verification

Who:
Real Intent, Inc., the innovator in automating the intelligence of formal technologies for electronic design verification, announced today that Jin Zhang is presenting at the Design Automation Conference (DAC09) on the topic of formal verification.

Ms. Zhang is an award winning author, and will talk about how to “Unleash the Power of Formal Analysis for Clock Domain Crossing (CDC) Verification.” She has over 12 years of experience working in the EDA industry, driving the effort of bringing new products to market. At Real Intent she is a Technical Marketing Manager. Ms. Zhang received her PhD from the Electrical and Computer Engineering department at Portland State University (PSU) in 2006. Her research paper received the IEEE 2008 D. O. Pederson best paper award.

What:
Unleash the Power of Formal Analysis for CDC Verification
People often think of formal verification as equivalence checking or model checking. Formal techniques can be applied to a wide variety of applications. In this presentation, we will look at the application of formal techniques to clock domain crossing (CDC) verification. Critical design errors can be detected by performing formal analysis on the data and control crossings of the design. Examples will be presented to demonstrate the power of formal techniques for CDC verification.

When/Where:
Wednesday, July 29, 1:00pm - 3:00pm
Booth #4359, North Hall
Moscone Convention Center, San Francisco, California

About Real Intent‘s Automatic Verification Software
Real Intent’s automatic verification solutions include Ascent™, the complete solution for early functional verification; Meridian, the most precise, comprehensive and innovative CDC solution in the market; and PureTime, the best-in-class, comprehensive constraints validation solution with glitch-aware exception verification.

About Real Intent
Real Intent is the innovator of automating the intelligence of formal techniques for design verification. This technology is being used to solve critical problems encountered by design and verification teams worldwide. Real Intent’s family of products dramatically improves the functional verification efficiency of leading edge ASICs and FPGAs devices.

Real Intent is headquartered at 505 North Mathilda Avenue, Suite 210, Sunnyvale, CA 94085, phone: (408) 830-0700 fax: (408) 737-1962, web: www.realintent.com, e-mail: info@realintent.com

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Real Intent Contact
Carol Hallett
VP of Worldwide Sales and Marketing
+1-408-830-9303
carol@realintent.com

Press contact:
Georgia Marszalek
Valley PR LLC for Real Intent
+1-650-345-7477
Georgia@ValleyPR.com

Note to editors: A photo is available on request.

Ascent, Meridian, and PureTime are trademarks of Real Intent, Inc.
All other trademarks and trade names are the property of their respective owners.