Real Intent Announces New Functional Verification Capabilities and Celebrates Technology Growth at DAC09
San Jose, California – June 29, 2009-
Real Intent Inc. will celebrate growth
in the number of verification solutions and the technologies embedded in them at the
Design Automation Conference (DAC09) in San Francisco next month by showcasing its family of
products—
Ascent™ for early functional verification,
Meridian™, the innovative Clock
Domain Crossing (CDC) solution, and
PureTime™ for comprehensive constraints validation.
Real Intent’s automatic verification solutions use innovative formal techniques to solve
critical design and verification problems in an easy to use methodology, resulting in
comprehensive error detection and high return on investment.
About Ascent and What’s New
Ascent is the complete solution for early functional verification. The Ascent family now includes a new and
improved
Ascent Lint for smart policy-based lint checking; and a new
Ascent PBV for Path-Based verification
to achieve desired design connectivity and to ensure X-robust design to prevent and debug Register Transfer
Level (RTL)/netlist mismatches;
Ascent IIV for comprehensive Implied Intent Verification; and
Ascent ABV
(formerly called Conquest) for static formal Assertion-Based Verification. Ascent promises to detect 50%
of design errors in the early functional development stage with little investment.
Real Intent’s Other Flagship Products
Meridian is the most precise, comprehensive and innovative CDC software in the market.
Meridian CDC offers high
performance structural and formal clock intent analysis, with links to enable dynamic CDC verification in
simulation through
Meridian SimPortal. Meridian CDC’s advanced formal technology ensures correct CDC operations
on every crossing and handles free running clocks. Meridian supports both RTL and netlist.
Meridian FPGA is the
CDC solution for FPGA designs.
PureTime is the best-in-class, comprehensive constraints validation solution with glitch-aware exception
verification.
PureTime Constraints performs syntax and semantic checks on design constraints, such as clock, IO,
timing checks, downstream tool capability and version checks.
PureTime Exceptions formally verifies false path and
multicycle path exceptions with concise reporting to allow easy debugging.
Prakash Narain, President and CEO at Real Intent, commented, “We are very pleased with the growth of our product offerings to meet the increasing verification challenges faced by our customers. Our three product families cover functional and timing closure verification from early design stage to implementation. It is an exciting time for us to grow our technology and our business. We are happy to celebrate our growth with the design community at DAC.”
About Real Intent
Real Intent is the innovator of automating the intelligence of formal techniques for design verification. This technology is being used to solve critical problems encountered by design and verification teams worldwide. Real Intent’s family of products dramatically improves the functional verification efficiency of leading edge ASICs and FPGAs devices.
Real Intent is headquartered at 505 North Mathilda Avenue, Suite 210, Sunnyvale, CA 94085,
phone: +1 (408) 830-0700 fax: +1 (408) 737-1962, Web:
www.realintent.com, e-mail:
info@realintent.com,Twitter:
RealIntent.
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Real Intent Press Contacts
Carol Hallett
VP of Worldwide Sales and Marketing
+1-408-830-9303
carol@realintent.com
Georgia Marszalek
ValleyPR LLC for Real Intent
+1-650- 345-7477
Georgia@ValleyPR.com
Ascent, Meridian and PureTime are trademarks of Real Intent, Inc.
All other trademarks and trade names are the property of their respective owners.