Munich, Germany, Design Automation & Test in Europe (DATE) Conference–
March 8, 2005 – Real Intent, Inc., the leading supplier of formal verification software, based in Santa Clara, Calif., today introduced PureTime, a software timing exception prover (verifier) that extends the company’s formal technology to address design implementation challenges.
PureTime solves an important electronic design problem by proving the correctness of timing exceptions created by designers using 100% exhaustive analysis. Errors in timing exceptions can create schedule delays, chip re-spins, or failing hardware in the field. The later these problems are discovered, the more expensive they become, making it imperative to use PureTime’s automatic verification early, and whenever exceptions change.
Extending the reach of formal technology
“Our vision is to leverage our formal technology in innovative ways, to solve key design problems. We continue to extend the reach of formal analysis, from functional verification, to ensuring that timing issues are detected and removed from designs.”, said Prakash Narain, Founder and CEO of Real Intent. “PureTime moves us into the timing closure space, and like our Verix products, it increases designer productivity.”
About Timing Closure
In order to reach timing closure, engineers manually create Synopsys Design Constraint (SDC) files, which define false-path and multi-cycle paths. These timing exceptions guide timing and synthesis tools, through identifying timing paths which do not need to complete in a single clock cycle. This manual exception creation can introduce errors that remain unchecked using traditional verification methods. PureTime exhaustively proves the correctness of these exceptions to improve productivity and quality, and meet time to market goals.
More About PureTime
Input to PureTime includes structural descriptions, RTL, and SDC files. Paths defined as false paths are proven to never affect the design output. Paths defined as multi-cycle paths are proven to only affect the output in the number of clocks specified. When PureTime determines that an exception is incorrect, counter examples are provided to guide the designer to the exact location and time where the problem occurs in the design.
PureTime supports both VHDL and Verilog.
Other Solutions from Real Intent
The Verix™ family is a set of state of the art verification tools, built upon a single unified database. Verix software products utilize the power of formal analysis to verify design assertions and either prove them correct or detect bugs that are hard to find. Verix can detect defects entirely missed with other Register Transfer Level (RTL) verification techniques. A combination of highly optimized formal engines and patented automatic design partitioning gives Verix the industry's largest formal capacity and proof capability. The Verix family includes Expressed Intent Verification (formal assertion based verification), Clock Intent Verification (metastability and hazard detection), and Implied Intent Verification (automatic design verification).
About Real Intent
Real Intent is the leading provider of assertion-based verification (ABV) solutions, and is extending breakthrough formal technology to critical problems encountered by design and verification teams worldwide. Real Intent’s Verix products dramatically improve the functional verification efficiency of leading edge application-specific integrated circuit (ASIC), system-on-chip (SOC), and Field Programmable Gate Array (FPGA) devices. Over 30 major electronics design houses, including Sun Microsystems, ATI, Agilent Technologies, nVidia, and NEC Electronics, rely on the Verix software. Founded in 1999, Real Intent is a privately-held Electronic Design Automation (EDA) company headquartered in Santa Clara, CA. For further information, visit www.realintent.com. |
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