| Utilizing Assertions To Improve Embedded Systems, IP Verification Productivity To Be Revealed To Designers, Verification Engineers | ||||||||||
| LOS ALTOS, Calif., and SANTA CLARA, Calif., May 28, 2002 –– A hands-on tutorial to train hardware designers on assertion-based validation for intellectual Property (IP)-based embedded system verification will be held during the 39th Design Automation Conference (DAC) at the Ernest N. Morial Convention Center in New Orleans. The tutorial will be held Tuesday, June 11, from 2-5 p.m. in Room 293. It is presented by Co-Design Automation, Inc., a provider of electronic system simulation, Real Intent, Inc., a leading supplier of assertion-driven formal verification software. Setup for designers to get hands-on experience, the tutorial will use available software, demonstrating a formal functional verification and system simulation environment for implementing IP within an embedded system. Designers will utilize assertions across an embedded system, learning how to quickly verify IP blocks standalone with formal verification tools, and reuse the same test structures within an IP-based platform, driven by hardware and software tests. Benefits of combining formal verification and system simulation, as well as the application of software-driven platform verification, will be demonstrated. Focus will be placed on Co-Design and Real Intent Superlog® Assertions (CRSA), recently donated to Accellera for inclusion in the SystemVerilog standard. A standard ARM-based platform will be used with the ARM core operating an AMBA bus interfacing with the IP. Registration may be done online at www.dac.com About Real Intent Real Intent, headquartered in San Jose, California, offers award-winning assertion-driven formal verification products for electronic design. These products give users the capability of comprehensively verifying designs early and significantly reduce the cost of verifying integrated circuits, electronic systems and systems on a chip (SoC). |
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