Real Intent Ships Verix

Verix Verifies RTL Without Testbenches, Frees Designers from Testbench Limitations NVIDIA Among First Customers

SANTA CLARA, Calif., July 4, 2000, Real Intent Inc., an electronic design automation (EDA) company that is creating an Intent-Driven Verification (IDV) approach that fundamentally alters functional verification methodology, announced that its first product, Verix, is shipping.

Verix, announced in May, verifies a design by ensuring that its implementation is consistent with the designer's intent. Real Intent’s breakthrough technology promises to revolutionize functional verification by eliminating large classes of design errors (or Intent Violations) without the need for testbenches.

Stephen R. Pollock, Vice-President of Marketing at Real Intent, noted, “Testbenches are difficult to write and reuse. With Verix, designers can verify their designs, early in the design cycle, without a testbench and as soon as an RTL file is saved. In this way, they eliminate many verification problems prior to simulation and synthesis runs and dramatically reduce their verification time.”

Verix analyzes the RTL description, extracts the Implied Design Intent, verifies it with Exhaustive Sequential Analysis, reports 100% reliable results for any violations, and generates a VCD trace for easy debugging. Verix can be used throughout the verification cycle even as the RTL is being modified. This keeps the RTL free of a large class of Intent Violations. Real Intent will release Verix-Pro, a product upgrade that verifies Expressed Design Intent later this year.

Customer Acceptance
Chris Malachowsky, Founder and VP of Engineering, of NVIDIA (Santa Clara, CA), said, “Given the complexity and sheer size of our 3D processors, effective design verification enhances our ability to deliver products on time. We use Verix to find and eliminate errors early in the design cycle, even before the first testbenches are built. With the combination of its low learning curve and its high coverage and capacity, Verix quickly became a valuable part of our verification methodology. Intent-Driven Verification applied hierarchically across a full-chip’s functionality promises to revolutionize design verification.”

Verix Features
Verix analyzes the RTL and detects classes of Intent Violation that typically result in design errors. These Violations are very common in early phases of the design. Verix performs exhaustive sequential analysis to examine the Intent Violations and reports 100% reliable results. Where applicable, Verix generates a complete VCD trace for easy debugging. The following is a representative list of intent violations detected by Verix:

Conflicting Assignment
Identifies if a net within a design has multiple drivers that can cause conflicting logical values simultaneously.
Block Enable
Identifies if the enabling condition for a code block can never be met.
Parallel Case
Identifies if a condition exists which can map the case variable to more than one of the defined case labels for a parallel case pragma case statement.
Full Case
Identifies if a condition occurs that can map the case variable to a value other than one of the defined case labels or a case statement with a full case pragma.
Static X-Source
Identifies conditions in which a logical net does not have a known driven value.
Non-Resettable Flops
Identifies flip-flops that fail to initialize to a known value.
Range Violation
Identifies if a vector can be indexed out of range.

Availability
Verix is available now for Verilog and Sun or HP workstation users.

About Intent-Driven Verification
Real Intent has pioneered a new intent-driven design verification approach that has the promise to revolutionize functional design verification. Real Intent's goal is to develop easy to use products that verify that the design implements the designer's intent, at the earliest opportunity in the design cycle. These products enable the chip designs to rapidly reach quality goals with dramatically reduced effort. They address the problems with the conventional simulation based approaches that are testbench limited and require a large amount of resources to drive the simulation and debugging process.

About Real Intent
Real Intent’s goal is to develop technology for intent-driven validation. The company is focused on developing tools that streamline the verification process and achieve quality levels rapidly and early in the design cycle with reduced resources.