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Real Intent May 2015
                Verification News

Real Verification News September 2015

New Release of Meridian CDC, X-prop Tech Note, Fall Events

In this issue, we present the new 2015 release of Meridian CDC for clock-domain and reset-domain crossing sign-off, give a preview of our new X-propagation technical paper, and review our fall events.

Thoughts From Prakash Narain, President and CEO…

Most functional verification for SoC and FPGA designs is done prior to RTL hand-off to digital synthesis, since gate-level simulations take longer to complete and are significantly harder to debug.  However, gate-level simulations are still needed to verify some circuit behavior.  Unfortunately, X’s in gate-level simulations can cause differences in the RTL simulation output and the gate-level simulation output.  X’s generally exist in all designs – it can be difficult to prevent this for practical reasons.  Simulation results may be different because of X’s that are hidden in the RTL simulation by X-optimism, or additional X’s may exist due to X-pessimism in gate-level simulations. Pessimism can be fixed by overriding the simulator because you know that real hardware would always resolve to a deterministic value. The challenge is confirming that the X value is a result of X-pessimism and not simply X-propagation, and then forcing it to the right value at the right point in time so the simulation matches that of real hardware. 

Real Intent's Ascent XV product corrects X-pessimism on the fly so the simulation is hardware accurate. Use of Ascent XV saves the time required to get gate-level simulations started by an order of magnitude.  It is proven to be superior to alternative approaches in the marketplace in terms of performance, memory, and accuracy.  Its ease of use and capacity, make it the only practical solution for large SoC designs, just like our other Ascent and Meridian products.

New Meridian CDC Release with Next-Generation Features

This month we delivered the latest 2015 release of Meridian CDC for comprehensive clock-domain crossing (CDC) and reset-domain crossing (RDC) analysis. This new software release adds enhanced speed, analysis and debug support, boosting productivity for SoC and FPGA design teams. With a brand new way to debug CDC violations, it lets you achieve giga-gate capacity verification without sacrificing precision. We believe it is the industry’s fastest-performance, highest-capacity and most precise CDC solution in the market.

Some of the features of the latest Meridian CDC include:
  • 30% faster performance and improved capacity for Giga-gate SoCs
  • iDebug: a state-of-the-art design intent debugger and analysis manager
  • Interfaces based approach for low-noise CDC analysis
  • Qualitative improvements for several CDC checks
  • Tcl-based command line interface lets user query and create custom scripts for debug and reporting
  • New formal analysis engine with up to 10X faster speed and greater coverage to find CDC problems
  • New HTML documentation improves usability
For additional insights and comments, please watch a video interview here.

Come Visit Us at Upcoming Industry Events

During October and November we will exhibit our Ascent and Meridian solutions at major industry events in Japan, China, Europe and Israel. We hope to see you at Design Solution Forum in Yokohama, Japan, on Friday, Oct. 2. Or join us at the International Conference on ASIC (ASICON 2015) Nov. 3-6 in Chengdu, China, where Ramesh Dewangan, our VP of Product Strategy, will present a 90-minute tutorial; “New Challenges and Techniques for Clock Domain Crossing and Reset Sign-off.” You can also see our advanced sign-off solutions at the DVCon EU technical conference in Munich on Nov. 11-12, in area F4, and at SemIsrael in Airport City on Nov. 17.

A Practical Solution to Fixing Netlist X-Pessimism

A new technical paper discusses the causes of X-pessimism in designs, current methods to eliminate or control it (with their shortcomings) and introduces Real Intent's Ascent XV- Netlist Pessimism product.

Ideally, the output of the RTL simulations will match the output of gate-level netlist simulations on the same design after synthesis.  And why wouldn’t they?  Besides the obvious things that are being verified in your gate-level simulations, there are also unknown values (X’s) that were not seen in RTL due to X-optimism, and additional X’s in the gate-level simulations due to X-pessimism. This paper focuses on the issues of X-pessimism at the netlist level.  X-pessimism is described, current solutions are discussed, and an Ascent XV- Netlist solution is presented.

Click on the hyperlink A Practical Solution to Fixing Netlist X-Pessimism to read the paper.

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Video Update

Video: New 2015 Lint

Video: New 2015 Lint

Video: New 2015 Lint

In the News

Real Intent Delivers Major Innovation in Clock Domain Crossing Sign-off
of SoC Designs

Upcoming Events

Design Solution Forum, Yokohama, Oct. 2

ASICON, Chengdu, China, Nov. 3-6

DVCon Europe, Munich, Nov. 11-12

SemIsrael Expo, Nov. 17

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