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Real Intent February 2014 Verification News

February 2014

New Ascent IIV Release, Exhibiting at Events, New VP of Application Eng.

The New Year is starting with a new release of the Ascent IIV automatic functional verification tool with several new features and enhancements. Details are below. We are exhibiting at Design and Verification Conference and Exhibition (DVCon), the Cadence User Conference (CDNLive) and the Synopsys User Group (SNUG), all in Silicon Valley, California. We will also be exhibiting and presenting a talk on clock domain crossing (CDC) verification at the ChipEx Microelectronics industry conference in Tel Aviv, Israel.  We also are very pleased to announce our new vice-president of Application Engineering.

Work Smarter Not Harder for SoC Sign-off

- Prakash Narain, President and CEO

With the Design and Verification Conference right around the corner, it’s a good time to look at Real Intent’s core expertise – SoC sign-off. Along with the continuing need for verification in different application areas, there’s an ongoing need for smarter reporting – analysis that provides a more expanded and deeper understanding of your intent as a designer. We know you are looking for verification reports that are organized in an easy way for review and design debug, so you’re not left drowning in data from the analysis of CDC, Lint checks, hardware reset and initialization, and automatic intent verification. All these reports should present the key issues and let you drill down hierarchically.

A potential hazard of automated intent checking is that the tool may not prioritize the errors that really matter. An problem in one condition in part of the RTL may trigger a number of ancillary errors that the tool dutifully reports, but which obscure the root cause that, if fixed, will also solve many of the secondary problems. This is where smart reporting will play an important role.

Smart reporting looks one level deeper at the design and assembles the errors that really matter so that the designer is not forced to wade through a series of reports that, in reality, are simply shadows of the root cause.
SoC sign-off requires innovation not only in the engines, but in organization. Our Meridian and Ascent verification tools are unsurpassed in helping you get to sign-off quickly so you can put your ingenuity into play in the market place.

Real Intent Unveils Major Enhancements in Ascent IIV for Early Functional Verification of Designs

Ascent IIV is a state-of-the-art automatic RTL verification tool. No test bench is needed by the tool, making it easy and efficient for designers to find RTL bugs earlier in the design flow before they become more expensive to uncover. It finds bugs using an intelligent hierarchical analysis of design intent. The analysis minimizes debug time by identifying the root cause of issues and provides the VCD traces that show the sequence of events that lead to an undesired state.

Our new 2014 release delivers several major enhancements to finite-state machine (FSM) analysis and debug including:
  • Improved root cause analysis minimizes time spent debugging FSMs
  • New FSM transition checks for deeper analysis of the design
  • New FSM debug reporting with direct trace back to state transition assignments
  • SystemVerilog 1800-2009 language support for easier adoption into existing design flows
Click here to read further details in the announcement.
For insights on trends in verification and comments on the new features from Chris Morrison, chief architect, please watch a video interview here.

Real Intent Names Ramesh Dewangan VP of Application Engineering

On February 17, Real Intent announced the appointment of verification sign-off expert Ramesh Dewangan as vice president of Application Engineering. Ramesh will oversee Real Intent's Application Engineering (AE) team that supports the sales team and customers. He brings a wealth of understanding of customer requirements for verification success and design sign-off to his new role.

Ramesh gave the following comments on joining Real Intent: "My extensive experience with RTL sign-off in my career convinced me that the market has seen only the tip of the iceberg in terms of what's needed for the sign-off of billion-gate SoCs. I'm thrilled to be part of this exciting results-oriented team that is truly breaking new ground in SoC sign-off. I look forward to expanding Real Intent's base and supporting our customers worldwide with the industry's most effective verification solutions."
Click here to read further details in the announcement.

Semiconductor Engineering's Video Chalk Talk with Dr. Roger B. Hughes

Recently, Ed Sperling, Editor-in-Chief of Semiconductor Engineering interviewed Roger Hughes, director of strategic accounts at Real Intent. Ed asked Roger about problems in verification, what's changing in verification as design complexity increases, where engineers typically make mistakes, and what clock domain crossing/checking really means and what the issues are for very large designs. Watch and get answers for things like how to avoid false design warnings in this whiteboard chalk talk at: http://www.realintent.com/real-talk/1016/video-tech-talk-changes-in-verification.

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Video Update
Lending a Hand to CDC..., Verification Futures Conf. Presentation, Nov. 2013

In the News

Real Intent Unveils Major  Enhancements in Ascent IIV for Early Functional Verification of Digital Designs

Real Intent Names Ramesh Dewangan VP of Application Engineering

NEC Adopts Real Intent Automatic Verification to Improve Design Quality

Upcoming Events

Design & Verification Conference & Exhibition, San Jose, CA, Mar. 3-6

CDNLive, Silicon Valley, March 11-12

SNUG, Silicon Valley,
March 24-26

  ChipEx Microelectronics Conference, Israel, April 30

Real Intent, Inc. 990 Almanor Ave., Suite 220, Sunnyvale CA 94085

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