The folks at Altera have unveiled their Quartus II software version 8.1 for CPLD, FPGA, and HardCopy ASIC designs. Based on internal benchmarks, the folks at Altera claim high-density FPGA compile times three times faster than other FPGA-vendor supplied development software.

Faster design development
While next-generation FPGAs deliver a greater level of functionality, design teams continue to be constrained by limited development times. Quartus II software version 8.1 helps speed development times by automating traditionally time-consuming features.

The design partition planner, introduced in the previous version of Quartus II software, now provides automated partitioning in version 8.1, allowing more designers to leverage the productivity benefits of incremental compilation.

Quartus II software now also eliminates the need to modify gated clocks manually by automatically converting gated clocks (as used in RTL intended for an eventual ASIC deployment) to functionally equivalent logic supported by the FPGA architecture. Automating these features allows design teams to focus more effort on value-added portions of the design.

Expanded device support
Altera launched its high-performance, high-density 40-nm Stratix IV FPGAs in May 2008. To date, nearly 600 customers are part of Altera's Stratix IV early adopter program, and many have started designing Stratix IV FPGAs into applications across all of Altera's market segments using Quartus II software.

Version 8.1 provides an even greater level of support to these customers by adding Stratix IV pin-outs and support for a new Stratix IV FPGA speed grade offered in a low-cost package. The software provides added transceiver timing-model support, as well as support for 8.5-Gbps transceivers, 1.6-Gbps LVDS and 400-MHz DDR memory. For designers targeting a HardCopy ASIC implementation, Quartus II software provides initial support for HardCopy IV ASICs.

New features in Quartus II software version 8.1

* SignalTap II Embedded Logic Analyzer - Finer data-sampling control speeds debugging and improves on-chip memory efficiency.
* Enhanced SOPC Builder Tool -
o New HDL templates enhance the speed and ease for which SOPC Builder can be used for intellectual property (IP) reuse.
o A new Avalon memory-mapped half-rate bridge is available for low-latency access for DDR SDRAMs.
* New operating system support - Red Hat Enterprise Linux 5 and CentOS 4/5 (32 bit/64 bit) are now included.
* Enhanced third-party simulation interface - The interface supports automatic compilation of library files for faster simulation setup.
* New Pin-Out Advisor - The advisor guides pin-out creation and interface with third-party board tools.
* Real Intent Verification Support - Real Intent's Meridian FPGA Clock Domain Crossing (CDC) software offers easy-to-use automatic clock intent verification to catch design errors and create confidence in reliable CDC operations.
* New and enhanced IP cores and megafunctions - Digital signal processing (DSP), memory and protocols accelerate development.
* Physical synthesis engine enhancements - Improve performance of timing-critical blocks in 20 percent less time on average than the previous version for faster timing closure.
* Synopsys Design Constraints (SDC) - SDC templates guide and accelerate timing constraint creation.

Pricing and availability Both the subscription edition and the free web edition of Quartus II software version 8.1 are now available for immediate download (www.altera.com/download). The Subscription Edition is also available in DVD format by request (www.altera.com/dvdrequest).

Altera's software subscription program simplifies obtaining Altera design software by consolidating software products and maintenance charges into one annual subscription payment. Subscribers receive Quartus II software, the ModelSim-Altera edition, and a full license to the IP Base Suite, which includes 11 of Altera's most popular IP (DSP and memory) cores.

The annual software subscription is $2,495 for a node-locked PC license and is available for purchase at Altera's eStore (www.altera.com/buy) or from authorized distributors.

For more information about Quartus II software version 8.1 visit www.altera.com/quartus2.

About Real Intent

Real Intent is extending breakthrough formal technology to critical problems encountered by design and verification teams worldwide. Real Intent’s products dramatically improve the functional verification efficiency of leading edge application specific integrated circuit (ASIC), system-on-chip (SOC), and Field Programmable Gate Array (FPGA) devices. Over 40 major electronics design houses, including AMD, NVIDIA, and NEC Electronics use Real Intent software.

 

Real Intent is headquartered at 505 North Mathilda Avenue, Suite 210, Sunnyvale, CA 94085, phone: (408) 830-0700 fax: (408) 737-1962, web: www.realintent.com, e-mail: info@realintent.com.