Real Intent’s PureTime™ purchased by QLogic;
Sign-off timing exception verifier replaces manual review

SUNNYVALE California –– November 21st, 2006 –– Real Intent, Inc., the leading supplier of formal verification software for electronic design, announced today that its formal timing exception verifier software, PureTime, has been purchased by QLogic, a leader in storage area networking products. PureTime is used to remove the risk of timing exception errors, as well as reducing schedule risks when compared to a manual review process.

“With PureTime, we can improve our design quality and designer productivity in a quick automated way,” said Tom Paulson, Principal Engineer at QLogic. “Relying on a manual review process for timing exceptions is slow, labor intensive and open to human error. By introducing PureTime into our flow, we improved our design confidence and turnaround time. We chose PureTime because it gives us a complete standalone solution from a single provider, which verifies both false and multi-cycle paths.”

“The verification of timing exceptions is a clear need for the electronics design industry. Companies are increasingly relying on them in complex hardware design, and the lack of automatic verification of their correctness is a major concern to our customers,” said Rich Faris, Vice President of Marketing and Business Development, Real Intent. “Our solution enables users to get more out of their silicon, while removing functional and schedule risks associated with using unproven exceptions.”

About PureTime

PureTime is a software timing exception verifier that detects timing exception errors that create schedule delays, chip respins or failing hardware. Using exhaustive formal analysis, it proves the correctness of Synopsys Design Constraint (SDC) false-path and multi-cycle path exceptions. These exceptions can be created by designers, or received as a part of Intellectual Property (IP). PureTime works throughout the entire design flow, with both RTL and netlist designs. PureTime includes comprehensive exception
linting capabilities, and is glitch and interaction aware for highest accuracy.

About Real Intent:

Real Intent is extending breakthrough formal technology to critical problems encountered by design and verification teams worldwide. Real Intent’s products dramatically improve the functional verification efficiency of leading edge application-specific integrated circuit (ASIC), system-on-chip (SOC), and Field Programmable Gate Array (FPGA) devices. Over 40 major electronics design houses, including Sun Microsystems, ATI, Marvell Technology Group, nVidia, and NEC Electronics, use Real Intent software

Real Intent is headquartered at 505 North Mathilda Avenue, Suite 210, Sunnyvale, CA 94085, phone: (408) 830-0700 fax: (408) 737-1962
e-mail: info@realintent.com

Notes to editors;
Graphics and/or screen shots available on request.
Real Intent, Inc.
505 North Mathilda Avenue,
Suite 210
Sunnyvale, CA 94085
tel: (408) 830-0700
fax: (408) 737-1962
email: info@realintent.com
web: www.realintent.com
Vice President of Marketing &
Business Development
Rich Faris
(408) 830-0700 x212
rich@realintent.com
Georgia Marszalek
Valley PR
(650) 345-7477
Georgia@valleypr.com
EnVision, Conquest, Ascent, Convergence Engine, SimPortal, PureTime, Clock Intent Verification are trademarks of Real Intent, Inc. All other trademarks or registered trademarks are property of their respective owners.

Copyright® 2005 Real Intent, Inc.