|
|
|
|
|
| Real Intent Adds Formal Clock Intent Verification to Verix |
|
|
| Formal Verification Assures Reliable Data Transfer Between Clock Domains |
|
SAN JOSE, Calif., May 28, 2002 –– Real Intent, the leading supplier of assertion-driven formal verification software, announced today that the Company has added formal Clock Intent verification to its flagship product Verix.
Assertion-based formal Clock Intent verification analyzes and exhaustively verifies the stability and correctness of data transfer between clock domains.
What's New
According to Dr. Prakash Narain, Real Intent's President and CEO, "Verix now brings the exhaustive confidence of assertion-driven formal verification to verify the stability and correctness of data transfer between clock domains." Verix Clock Intent verification automatically identifies the clock domains and the hazards for signals crossing those domains. It further advises the designer about appropriate assertions to formally verify the data transfer. All the user needs to supply is the RTL and to identify clocks.
The Verix Clock Intent verifier looks at the RTL design description and automatically identifies the clock domains within the design and the signals crossing the clock domains. In addition, it identifies the absence or presence of synchronizers at the clock domain boundaries, and determines Verix assertions that can exhaustively verify the data transfer stability across the clock domain boundaries.
About the Clock Domain Verification Problem
The challenge of safe data transfer between clock domains is a common and difficult problem facing designers of SoCs and ASICs where data producers and data consumers run at different clock rates. The problem is caused at the systems level when multiple clock domains exist between high-speed processors and lower speed peripherals and in modern communication systems with multiple data sources running at different asynchronous clock rates. Designers employ a variety of clocking schemes to generate these synchronous and asynchronous clocks. Then, the designer must verify reliable data transfer for all possible combination of conditions. The exhaustive nature of assertion-driven formal verification is ideally suited to verify this kind of problem. Typically, it is difficult to model and verify these problems in simulation as the development of a test bench that exercises every possible combination of signals is a very daunting task.
How Verix Addresses Clock Intent Verification
The Verix Clock Intent verifier looks at the RTL design description and automatically identifies the clock domains within the design and the signals crossing the clock domains. In addition, it identifies the absence or presence of synchronizers at the clock domain boundaries, and determines Verix assertions that can exhaustively verify the data transfer stability across the clock domain boundaries.
More About Verix
Verix is Real Intent's pioneering assertion-driven formal verification system that verifies that a design is free from a large class of errors early in the design cycle, prior to simulation and synthesis. Verix features a number of formal verification innovations including: automatic checks, scalable hierarchical verification, in-line assertions and automatic generation of simulation checkers from formal assertions. Verix speeds the design of high-end semiconductors and systems-on-chip by formally verifying the design as the RTL is created.
About Real Intent and Assertion-Driven Verification Standards
In March, Real Intent and Co-Design announced the joint donation of their Design Assertion Subset (DAS) to Accellera.
Dr. Narain noted, "Real Intent is committed to Accellera's efforts for the standardization of assertions. Our active participation and support of Accellera's SystemVerilog standardization efforts underlines our mission to bring a standard verification methodology to our customers."
About Real Intent
Real Intent, headquartered in San Jose, California, offers award-winning assertion-driven formal verification products for electronic design. These products give users the capability of comprehensively verifying designs early and significantly reduce the cost of verifying integrated circuits, electronic systems and systems on a chip (SoC).
|
|
|
|
|
|
|
|
|
|
|
|
|
Copyright® 2005 Real Intent, Inc.
|
|
|
|
