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| Real Intent & Co-Design Automation Steer Industry-Wide Convergence On Assertions Through Accellera Donation |
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| Verilog-Based SUPERLOG Assertion Language Driven By Multiple Verification Companies |
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SAN JOSE, Calif., International HDL Conference, March 11, 2002 –– Co-Design Automation, Inc., a provider of electronic system simulation, and Real Intent, Inc., a provider of formal functional verification systems today donated the SUPERLOG® Design Assertion language Subset to the standards organization Accellera. The goal is to bring an industry-wide convergence on an efficient assertion language.
The Co-Design/Real Intent SUPERLOG Design Assertions Subset (DAS) will enable designers and verification engineers to write design checks using a standard language that can be applied to a broad range of tools without modification, improving verification productivity. It allows the efficient description of design assertions using a recognizable Verilog hardware description language (HDL)-based syntax, simplifying a range of applications. The donation includes automated verification capabilities embedded within Co-Design Automation's Systemsim™ system simulator, as well as formal model checking semantics contributed by Real Intent, derived from its Verix™ product line.
"Our combined extensive technical and customer experience in formal verification and simulation has allowed us to represent the customer perspective. Together with our partners, we have actively worked to design a unique assertion framework that addresses their needs," notes Dr. Prakash Narain, president and CEO of Real Intent. "This assertion standard enables a unified simulation and functional formal verification methodology which promises significant improvements in design verification throughput."
Other EDA vendors, including 0-In Design Automation, Inc., Novas Software, Inc. and Verplex Systems, Inc., also contributed time and resources to defining the SUPERLOG DAS, enabling its application across a broad range of verification technologies. The donation was further endorsed by verification companies Axis Systems, Inc., SynaptiCAD, Inc., Tharas Systems, Inc., Veritable, Inc.
"The time is right to establish an assertions standard usable by designers and verification engineers that may be applied throughout the design flow, and across a range of EDA tools," says Simon Davidmann, Co-Design's chief executive officer (CEO). "Our expertise in the simulation and verification space, together with that of our partners, has enabled a rich and powerful verification mechanism that dramatically reduces the time taken to establish correct design operation."
Dennis Brophy, chairman of Accellera and director of strategic business development at Model Technology, a Mentor Graphics (NASDAQ: MENT) company, agrees. "Many designers have started to utilize assertions in a wide range of tools; there is a clear need for an industry-wide standard in this area. Accellera addresses this need head-on and the donation of the Design Assertions Subset, driven by multiple companies, accelerates the creation of this standard."
For more details on Co-Design's standardization activities, contact Dave Kelf, Co-Design's vice president of marketing. He can be reached via email at davek@co-design.com or at (877) 6 CODESIGN, Ext. 404.
About Real Intent
Real Intent, headquartered in San Jose, California, offers award-winning assertion-driven formal verification products for electronic design. These products give users the capability of comprehensively verifying designs early and significantly reduce the cost of verifying integrated circuits, electronic systems and systems on a chip (SoC).
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Copyright® 2005 Real Intent, Inc.
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