|
|
|
|
|
| Design Verification Bottleneck Seminar Hosted by Tharas Systems, Real Intent and Co-Design Automation, September 18th, in Santa Clara, California |
|
|
|
|
Who
Verification leaders-Co-Design Automation, Real Intent and Tharas Systems-invite design and verification engineers and managers, who are designing complex, multi-million gate chips and systems to attend their seminar.
What
At the Verification Bottleneck seminar, attendees will learn how to reduce verification time and cost and see demonstrations of proven verification solutions.
Andy Bechtolsheim of Cisco and Atiq Raza of Raza Foundries will speak about how their respective companies are addressing the verification bottleneck and participate in a panel. Prabhu Goel, Chairman and CEO, Tharas Systems; Simon Davidmann, CEO, Co-Design Automation; and Prakash Narain, PhD, President & CEO, Real Intent, will also speak at the seminar.
Where
Santa Clara Hilton, 4949 Great America Parkway, Santa Clara, California
When
September 18, 2001 9am-1pm
Registration Information To register visit http://www.tharas.com/seminar_reg.html
About the Co-hosts:
Tharas Systems develops and markets high performance verification systems to designers of complex integrated circuits and electronic systems. The Tharas solution leads to significant shortening of the verification cycle; the pay off is material reduction in time-to-market. Tharas Systems' patented hardware accelerator Hammer® is the only solution that speeds up both the simulation of the design as well as execution of the test bench. Simulation acceleration applies to behavioral, RTL, and gate level representations. Increasing verification complexity is one of the main challenges of designing complex integrated circuits and systems today. Founded in 1998, Tharas is privately held and funded by venture capital and private investors from throughout the electronics industry. Corporate headquarters is located at 3016 Coronado Drive, Santa Clara, Calif. 95054. Visit Tharas Systems at http://www.tharas.com.
Co-Design Automation is an EDA company focused on the efficient creation, implementation, and verification of system on chip (SOC) designs. In 1999, Co-Design announced the SUPERLOG system design language, now utilized by 15 partner companies. Its products -- SYSTEMSIM and SYSTEMEX -- are achieving success throughout the electronics industry worldwide in system platform and advanced verification applications. Corporate headquarters is in Los Altos, Calif. Telephone: (877) 6 CODESIGN. Facsimile: (408) 273-6025. Email: info@co-design.com. On-line information is found at its Web Sites: http://www.co-design.com and http://www.superlog.org
About Real Intent
Real Intent, headquartered in San Jose, California, offers award-winning assertion-driven formal verification products for electronic design. These products give users the capability of comprehensively verifying designs early and significantly reduce the cost of verifying integrated circuits, electronic systems and systems on a chip (SoC).
|
|
|
|
|
|
|
|
|
|
|
|
|
Copyright® 2005 Real Intent, Inc.
|
|
|
|
