SANTA CLARA, Calif., May 8, 2000, Real Intent Inc., a new electronic design automation (EDA) company that it is creating an Intent-Driven Verification (IDV) approach that fundamentally alters the way functional verification is done today announced its first products: Verix™ and Verix-Pro™.
These products, the first in a family of products, verify a design by ensuring that its implementation is consistent with the designer's intent. Their breakthrough technology promises to revolutionize functional verification by eliminating a large class of design errors (intent violations) and reducing the dependence on the need for testbenches and simulation runs.
Dr. Prakash Narain, co-founder and CEO of Real Intent said, "The Verix family of products is the result of a development effort that began when Rajiv (Rajiv Kumar, COO) and I co-founded the company in 1998. As EDA tool users, we were frustrated with conventional testbench limited approaches to verification. Our goal is to develop a new approach to design verification that operates by verifying that the designer's intent is consistent with the design implementation. IDV addresses the key problem with a testbench limited approach, where the verification begins too late in the design cycle and the debugging effort then becomes enormous."
Verix analyzes the RTL description, extracts the Implied Design Intent, verifies it under all possible input conditions and reports 100% reliable results for any violations. Verix can be used throughout the verification cycle even as the RTL is being modified. This keeps the RTL free of a large class of intent violations.
Verix-Pro uses design intent information provided by the user with the RTL description. It detects Expressed Design Intent violations. More details will be available with the product announcement later this year.
Both Verix and Verix-Pro can be used early in the design cycle as soon as RTL code is available.
The technology that drives IDV was developed at Real Intent and includes patent-pending technology in the areas of:
- An elegant yet simple method of capturing design intent
- Automatically identifying the Intent Gap
- Methods for reporting intent violations in an intuitive manner
- Automated method for full-chip verification from the automatic hierarchical assembly of verified blocks.
Dr. Narain added, "We are developing a very sophisticated verification technology. Our goal is to hide the complexity of the underlying technology from the user by investing in powerful automation techniques. Our beta results indicate that we are meeting that objective."
Verix Features
The classes of intent violations that Verix detects typically result in design errors, which are very common in early parts of the design. The intent violations are examined under all possible input conditions and 100% reliable results are reported. The initial release of Verix detects the following seven intent violations:
- Conflicting Assignment
Identifies if a net within a design has multiple drivers that can cause conflicting logical values simultaneously.
- Block Enable
Identifies if the enabling condition for a code block can never be met.
- Parallel Case
Identifies if a condition exists which can map the case variable to more than one of the defined case labels for a parallel case pragma case statement.
- Full Case
Identifies if a condition occurs that can map the case variable to a value other than one of the defined case labels or a case statement with a full case pragma.
- Static X-Source
Identifies conditions in which a logical net does not have a known driven value.
- Non-Resettable Flops
Identifies flip-flops that fail to initialize to a known value.
- Range Violation
Identifies if a vector can be indexed out of range.
Verix also produces vectors that can provide 100% state variable and assignment toggle coverage. These vectors can be used as part of a simulation-based verification strategy.
Availability
Verix is currently in beta and the production release is scheduled for July 2000 for Sun users.
About Intent-Driven Verification
Real Intent has pioneered a new intent-driven design verification approach that has the promise to revolutionize functional design verification. Real Intent's goal is to develop easy to use products that verify that the design implements the designer's intent, at the earliest opportunity in the design cycle. These products enable the chip designs to rapidly reach quality goals with dramatically reduced effort. They address the problems with the conventional simulation based approaches that are testbench limited and require a large amount of resources to drive the simulation and debugging process.
About Real Intent
Real Intent’s goal is to develop technology for intent-driven validation. The company is focused on developing tools that streamline the verification process and achieve quality levels rapidly and early in the design cycle with reduced resources.
