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May 14, 2015

 

Enter to Win and See the Latest Developments in
Ascent Static Verification and Meridian CDC Sign-off

Come and Play at Our Booth!You are invited to visit the Real Intent booth at the 52st DAC show in San Francisco.
Real Intent is known for having the fastest, highest-capacity verification tools for static functional analysis including Lint, and for advanced RTL sign-off of designs with multiple clock domains (CDC).

  • Complete our quick verification survey at the booth and you will be entered into drawings for a cool Roku 3 and a Kindle PaperWhite e-reader!
  • To celebrate faster verification and design, race your favorite high-performance car in one of our two GRID Arcade Racing Simulator, and get your License-to-Speed.
  • Visit the exhibits for both Real Intent and our 'License-to-Speed' partner: OpenText and enter to win several $100 Amazon Gift Cards, GoPro camera, Bose wireless sound system, and Beats Studio wireless headphones.

Our technical presentations will bring you up to date with our new product releases that have been proven on giga-gate SoC and FPGA designs. Click on the links to book your appointment at the Real Intent booth #1422.

Ascent Lint with 3rd Generation iDebug Platform and DO-254
We've taken the industry's fastest linter for cleaning your RTL to a new level. We will present the latest advances in design rules and debugging features including support for DO-254.
Schedule a Time.

Meridian CDC for RTL with New 3rd Generation iDebug Platform
Meridian CDC continues to advance its market-leading speed, capacity and low-noise analysis of asynchronous clock domains in SoC and FPGA designs. At DAC 2015, we present our new state-of-the-art design intent debugger and data manager; its intelligent hierarchical analysis of design intent makes finding subtle clock-domain crossings easy and efficient.  You will not want to miss seeing the future for advanced CDC sign-off.
Schedule a Time.

Ascent XV with Advanced Gate-level Pessimism Analysis
Ascent XV provides a comprehensive static solution for making an RTL design X-robust, which ensures that the performance and accuracy of your simulations is not impacted by X-effects.  At DAC, discover the very latest in reporting and debug including advanced gate-level pessimism analysis.
Schedule a Time.
 

Accelerate Your RTL Sign-off
Real Intent will present the elements of a best-in-class solution for the accelerated verification sign-off of SoC and FPGA designs. A full suite of static verification concerns will be covered including: syntax and semantic checking (lint); constraints planning and management; reset analysis and optimization; automatic intent verification; CDC sign-off; and X-safe design analysis.  Schedule a Time.

Advanced CDC - Hierarchical and Physical CDC for Giga-gate Designs
This presentation will cover an optimized “bottom-up” verification flow that provides hierarchical CDC reporting and sign-off management for giga-scale designs,
including glitch analysis at both RTL and gate-levels. Schedule a Time.

Next-Generation Meridian Constraints for SDC
SDC timing constraints management will be presented with a complete solution that uncovers incorrect and incomplete constraints along with exception verification. Schedule a Time.

Autoformal RTL Verification
Automatic verification of RTL blocks covering over 30 functional areas without writing assertions or testbenches will be presented. Schedule a Time.

FPGA Sign-off and Verification
FPGA designers will see a complete Lint and CDC verification flow that smoothly works with their existing Xilinx and Altera design suites. Schedule a Time.