JOB RESPONSIBILITIES

Real Intent Inc., seeks talented candidates to join a high caliber team working on a revolutionary approach for RTL functional verification. Responsibilities will include creating and verification of hardware designs using formal property verification, synthesis, simulation and debugging tools. Driving tools usability and methodology as regards RTL formal verification and assertion-based verification. Adding designs to regression and automation of regression. Other desired attributes include excellent coordination, and interpersonal skills, ability to work well in small teams.

EDUCATION:

     •  MS in EE / ECE or related field
     •  1 year of experience in using HDLs (Verilog/VHDL).



Email Resume To:
jobs@realintent.com

Or Mail to Human Resources at:
Real Intent
505 North Mathilda Avenue
Suite 210
Sunnyvale, CA 94085