JOB SPECIFICATION
Develops breakthrough formal software, in a fast-paced small team environment, to speed the electronic design process from design to implementation.
JOB REQUIREMENTS:
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Expert in software design with C, C++, VHDL and Verilog |
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Understand the digital design process and procedures |
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Practical knowledge of formal verification, simulation, and synthesis protocols |
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Excellent communication and presentation skills, both written and verbal. |
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Master of Science degree in EE/CS with 1 year related experience. |
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Knowledge in formal verification techniques, SAT based engines, BDD, Symbolic, ATPG |
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Ph.D. EE/CS. |
Email Resume To:
jobs@realintent.com
Or Mail to Human Resources at:
Real Intent
505 North Mathilda Avenue
Suite 210
Sunnyvale, CA 94085
