Innovating the Intelligence of Formal Techniques for Automatic Design Verification

SENIOR R&D ENGINEER

JOB SPECIFICATION
Develops breakthrough formal software, in a fast-paced small team environment, to speed the electronic design process from design to implementation.

REQUIREMENTS:

  •  Expertise in C/C++, Verilog and VHDL, digital design, simulation
  •  Knowledge in formal verification techniques, SAT based engines, BDD, Symbolic, ATPG
  •  Ph.D. EE/CS



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